Abstract: The current many-core micro architecture does not match the MapReduce run-time, so there exist problems such as the low throughput, and the fact that speedup cannot be proportional to growth of cores, which makes many-core chip system unable to get deserving computing capability. This paper aims to solve these problems and achieve huge computing capability in the high performance many-core chip system. Firstly, the executing module for many-core MapReduce was analyzed. Then, a new three-dimensional (3D) memory architecture was proposed based on DOT module which included the designs of network-on-chip, communication module, the procedure of accessing memory and access module for MapReduce. Experimental results have shown that compared with tile structure of many-core system, the throughput of 3D storage system-based many-core system can increase more than 1.2 times, the speedup is proportional to the number of cores.