Abstract: To improve the performance of arithmetic VLSI system, a kind of multiple-valued current-mode (MVCM) circuitry based on dynamic source-coupled logic is presented. With the circuitry, a design of the 4-quatrit quaternary adder is designed based on conditional sum addition, which implements 8-bit addition operation. The calculation speed of VLSI is improved by the use of conditional sum logic. The designed adder is evaluated by HSPICE simulation in a 0.18 μm CMOS technology with the supply voltage of 1.8 V. The results show that its power dissipation is about 2.8 mW, the delay of sum and carry is 0.689 ns and 0.452 ns respectively, and the transistor counts is 636.