Abstract: This article describes the design and performance of low power under-sampling and hold amplifier used in high speed analog-to-digital converter. The designed circuitry consists of full differential switched capacitor circuit, high speed bootstrapped switch with under-sampling function and two-stage amplifier with continuous common voltage feed-back. The layout of the circuits is plotted under SMIC CMOS 0.18μm 1P6M process with 3.3V supply. The performance of system shows that the SNDR can reach 47dB when the sampling frequency is 2MHz with the power of 1mW and the signal frequency is 2.01MHz (equivalent to 10kHz). The circuit can be widely applied in the FSK system.