Abstract: To satisfy high speed large capacity of data buffering in modern high-resolution radar and pre-triggering sampling in passive radar or passive time-of-arrival-location(TOA) system,the article presents an architecture to expand the buffering capacity and realize pre-triggering function using multi-first input first output(FIFO) in series,analyzes the timing between two level FIFOs,and presents a method for setting the programmable flag in FIFO.Practice demonstrates that,the capacity of buffering amounts to 2 MB,and the number of pre-triggering amounts to 1 MB.Further more,the functions can be switched by FPGA.The configuration is also fit for other kinds of FIFO having programmable flag.