Abstract: Studies issues in the finite state machine (FSM) design in PCI bus interface controllers. The PCI top-level block design is first presented in terms of the bus interface controller. The FSM model of target PCI bus interface controller is then provided based on PCI bus operation timing. The basic operation of the bus controller is described with the Altera's FLEX10K FPGA device and Verilog HDL, along with the function simulation and synthesis and the FPGA design of the PCI bus controller. This brings out the strong points of the FSM, such as its clear structure and easy maintance.