Verilog-VHDL Simulation Interoperability

A Verilog-VHDL translating method directed by simulation semantics is presented. Based on the analysis and comparison, three steps are taken to implement the translation. Through semantic analyzing and syntax tree reconstructing before translation, the main part of Verilog is supported. According to the level in the design hierarchy, the modules are translated in down-top order, and that results in a correct VHDL declaration-reference order. The translation rules of assignment statements and delay/timing constructs are also explained in detail. This method has been successfully implemented in the translator developed by the authors. The correctness has been validated by many examples.