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Yu Miao, Jiwei Huo, Ze Liu, Ying Gao, Chengfei Wang. Fast Rail Defect Inspection Based on Half-Cycle Power Demodulation Method and FPGA Implementation[J]. JOURNAL OF BEIJING INSTITUTE OF TECHNOLOGY, 2022, 31(2): 185-195. DOI: 10.15918/j.jbit1004-0579.2021.053
Citation: Yu Miao, Jiwei Huo, Ze Liu, Ying Gao, Chengfei Wang. Fast Rail Defect Inspection Based on Half-Cycle Power Demodulation Method and FPGA Implementation[J]. JOURNAL OF BEIJING INSTITUTE OF TECHNOLOGY, 2022, 31(2): 185-195. DOI: 10.15918/j.jbit1004-0579.2021.053

Fast Rail Defect Inspection Based on Half-Cycle Power Demodulation Method and FPGA Implementation

  • In this paper, a fast-speed and real-time online rail inspection method based on half-cycle orthogonal power demodulation algorithm is proposed. For this method, the power characters of detection signal which represent the degree of rail track can be calculated using only half-cycle detection signal because of the symmetry characteristic of detected sine signal and reference signal. The theoretical analysis, simulation results and experiment results show that the demodulation precision of proposed method is almost equal to fast Fourier transform (FFT) demodulation method and orthogonal demodulation method, but has high demodulation efficiency and less FPGA resources cost. A high-speed experiment system based on three coils structured sensor is built for rail inspection experiment at a moving speed of 200 km/h. The experiment results show that proposed method is more effective for rail inspection and the time resolution of proposed method is double of classic method that based on FFT and orthogonal.
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